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HSMC DVI
Features
- Digital Visual Interface Compliant (DVI 1.0)
- Supports resolutions from VGA to UXGA (1600x1200 and 1920x1080 [1080p@60])
- 25 - 165 Mhz Pixel rates
- EDID data reading/writing
- Monitor detection through Hot-Plug
- 15Mbps Optical S-PDIF TX and RX for digital audio connectivity
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The Bitec HSMC DVI interface card is designed to allow developers
access to high-quality, high resolution video signals in their FPGA designs.
It integrates both a DVI receiver and transmitter onto the same card giving
the flexibility required by high resolution image processing systems. Card is
shipped with source code examples.
The hsmc dvi daughter card also supports a serial eeprom for FPGA design security. Developers can distribute demonstrations of their IP locked to the hsmc bvdc card.
For more information click here.
The latest version of the HSMC DVI also hosts both TX and RX Optical interfaces for S-PDIF audio. Note: The board is completely backwards compatible with previos vesrions..
Downloads
| Synopsis |
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| Product Brief |
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| Schematics |
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HSMC DVI EDID Update
This sof updates the EDID EEPROM on the HSMC DVI board to correctly report 1080P@60 |
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DVI 1080P Loop-through C120 (Beta)
This reference design demonstrates a DDR2 SDRAM loopthrough of a 1080P@60. An input image on the DVI port is tripple-buffered through the top and bottom banks of DDR2 SDRAM before transmitting on the DVI output port.
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DVI 1024x768 Loop-through C25 Eval (Beta)
This reference design demonstrates a DDR SDRAM loopthrough of a 1024x768 image. An input image on the DVI port is tripple-buffered through the boards DDR SDRAM before transmitting on the DVI output port.
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Stratix III Dev Kit Pin allocation Tcl scripts
These script files assign the DVI board pins for the Stratix III Dev Kit. See file contents for instructions. |
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Re-visit reguarly for future updates and reference design releases.
Altera, MegaCore and the Altera and Cyclone logos are Reg. U.S. Pat. & Tm. Off. and marks of Altera in and outside the US
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