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DP Receiver IP
Features
- Support for 1,2 & 4-lane
- Support 1.62 & 2.7GB/s link rate
- 80B/10B Decoder
- 16-bit scrambler
- 6,8,10,12 & 16 bit color support
- Supports RGB, YCbCr Colorimetric Formats
- Autonomous AUX channel
- External or internal EDID
- AUX debug channel
- User selectable AUX register SoPC Interface
- SoPC Integration
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DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry
leaders (Intel, DELL, Apple etc) DisplayPort is not hindered by license and royalty fees.
The Bitec DisplayPort IP core for Altera GX devices offers a cost-efficient alternative to ASICs and enables DTV manufacturers to rapidly
develop and deliver displays offering a superior viewing experience within ever-shrinking product lifecycles.
The Bitec DP IP core accepts 1,2 or 4 lane at either 1.62 or 2.7 GB/s link rate. In accordance with the DP specification 1.1a, the core
will adapt and train to the transmitting source capability by exploiting the reconfigurable features of the Altera GX devices.
The core outputs Avalon Image stream compatible pixel and sync data for easy integration in to the Altera Image Processing Suit. An optional Nios II debug port is available to allow AUX message interrogation and core performance.
Bitec also offer a tailoring service for bespoke designs. For more information contact Bitec.
Altera, MegaCore and the Altera and Cyclone logos are Reg. U.S. Pat. & Tm. Off. and marks of Altera in and outside the US
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